With the development of the semiconductor technology, integrated circuits with higher performance and more powerful functions require enhancement of the element density, and the sizes of the components and spaces between the components need to be scaled further. Moreover, 32/22 nanometer technology has been an inevitable trend of the development of integrated circuits, and become a topic competitively studied by major international semiconductor corporations and research institutions. Also, the gate engineering for CMOS devices, the core of which is “high-k dielectric/metal gate” technology, is the most representative technique in 32/22 nanometer technology, and its relevant studies on materials, processes, and structures have been in progress widely.
By a metal gate integrated with a high-k gate dielectric material, a transistor having a high mobility channel has been realized. However, due to the high-temperature processes during the integration, the property of the interface between the metal and high-k insulating material is changed and oxygen vacancies are brought into the high-k gate dielectric material, which disadvantageously leads to increasing of the PMOS threshold voltage and deterioration of the device reliability. Thus, it has become a most important task in manufacturing a “high-k dielectric/metal gate” device to effectively control the PMOS threshold voltage. At present, a solution to lower the PMOS threshold voltage of a “high k-gate dielectric/metal gate” device by oxygen diffusion (see Symposium on VLSI technology Digest of Technical Papers, 2009) may be used. This solution is based on removing the sidewall spacer and diffusing oxygen into the high-k dielectric material from the sidewalls of the high-k/metal gate. However, this method needs to remove the sidewall spacer. Removal of sidewall spacer is rather hard to control and often damages the gate dielectric layer, the gate electrode, and the source/drain regions, and thus degrades the performance of the device.
Therefore, there is a need for a method to manufacture a semiconductor device and a corresponding device structure, in which the threshold voltage of a PMOS device can be lowered without causing damages to the device.